1. Field of the Invention
The present invention relates to a delay locked loop circuit with an improved jitter performance, and more particularly to a delay locked loop circuit using a phase mixer for improved jitter performance by using a phase mixer. The delay locked loop circuit according to the present invention can be applicable to a semiconductor memory device and more particularly to all semiconductor devices and computer systems requiring a delay locked loop circuit.
2. Description of the Prior Art
As generally known in the art, the delay locked loop (hereinafter referred to xe2x80x9cDLLxe2x80x9d) circuit is a clock generating device for compensating skew between an external clock and data, or an external clock and an internal clock. FIG. 1 is a block diagram illustrating an example of a conventional DLL circuit. An input buffer 101 in the conventional DLL circuit 100 receives and converts an external clock signal exCLK or a reference clock signal into an internal clock signal inCLK having a signal level suitable for an internal circuit. An variable delay circuit 103 receives the clock inCLK from the input buffer 101 and generates an output clock signal dIICLK by delaying for a predetermined time. A main phase determining circuit 105 receives the output clock signal dIICLK and the external clock signal exCLK and detects a phase difference between the two clock signals so that it generates a phase push signal PUSH when a phase of the output clock signal exCLK runs ahead of the phase of the external clock signal exCLK. In constrast, it generates a phase pull signal PULL when the phase of the output clock signal dIICLK lags behind the phase of the external clock signal. Although the main phase determining circuit 105 detects a phase difference between the output clock signal dIICLK and the external clock signal exCLK and generates the phase pull signal PULL or the phase push signal PUSH, since the circuit 100 in FIG. 1 is for arranging the output clock signal dIICLK and the external clock signal exCLK, there are possibilities for a plurality of variants of the main phase determining circuit 105 such as a circuit to use the internal clock signal inCLK and the output clock signal dIICLK as an input. A delay control circuit 107 receives the phase push signal PUSH or the phase pull signal PULL from the main phase determining circuit 105, generates a control signal CTRL for controlling a delayed amount of a variable delay line 104, and supplies the control signal CTRL to the variable delay circuit 103.
The DLL circuit 100 depicted in FIG. 1, as described above, corresponds to a case for obtaining an output clock signal dIICLK having a phase identical to the phase of the external clock signal exCLK. This can be achieved by properly adjusting the amount of the delay of the variable delay circuit 103. The main phase determining circuit 105 determines that the phase of the output clock signal dIICLK is slow by comparing the phases between the external clock signal exCLK ad the output clock signal dIICLK and activates the phase push signal PUSH. If the phase push signal PUSH is provided to the delay control circuit 107, the delay control circuit 107 generates the control signal CTRL which reflects the phase push signal PUSH, so that the amount of delay in the variable delay circuit 103 is slightly increased. The amount of the delay is increased little by little so that the phase of the output clock signal dIICLK will approach the phase of the external clock signal exCLK. In contrast, if the phase of the output clock signal dIICLK lags the phase of the external clock signal exCLK, the main phase determining circuit 105 activates the phase pull signal which results in the decrease of the amount of delay in the variable delay circuit 103 through the delay control circuit 107. Through the procedures described as above, the phase of the output clock signal dIICLK is adapted to the phase of the external clock signal exCLK. Under such conditions, the phase of the output clock signal dIICLK swings about the phase of the external clock signal exCLK at least by minimum variable delay amount (hereinafter referred to unit delay) to be increased or decreased by the phase push signal PUSH or the phase pull signal PULL.
The DLL has a variety of performance indices, one of the indices being jitter performance. The jitter means a swing amount as the phase of the DLL output signal reciprocates minutely. The less the amount of the jitter is, the superior the DLL is. Errors in the phase determining circuit and the unit delay of the variable delay line are restricted to factors affecting the jitter performance. Until now, the error and the unit delay have been used to enhance jitter performance by mainly improving each value thereof. FIG. 2 shows the jitter performance of the circuit in FIG. 1. When the phase of the reference signal is set to 0 (zero), the main phase determining circuit 105 should swing the phase of the output signal of the delay locked loop circuit 100 in FIG. 1 by at least the amount of error. When a maximum error of the main phase determining circuit 105 is set to xcex94PD, a jitter window, an error area due to the main phase determining circuit 105, is represented in the equation 1, and corresponds to portions indicated by "PHgr"P in FIGS. 2A and 2B.
|JW| less than xcex94PDxe2x80x83xe2x80x83[Equation 1]
where the jitter is increased by the unit delay tUD, it gets decreased due to the signals PUSH and PULL. When the jitter is increased toward the right side by the unit delay tUD due to the signal PUSH, as illustrated in FIG. 2A, the jitter window at that time is represented as equation 2. Meanwhile, as illustrated in FIG. 2B, when the jitter is increased toward the left side by the unit delay tUD due to the signal PULL, the jitter window thereof is represented as equation 3. Therefore, the jitter window becomes sum of the equations 2 and 3 finally and is expressed by equation 4. A maximum phase error "PHgr"MAX is expressed by the equation 5.
xe2x88x92xcex94PD less than JWa1 less than xcex94PD+tUDxe2x80x83xe2x80x83[Equation 2]
xe2x88x92xcex94PDxe2x88x92tUD less than JWb1 less than xcex94PDxe2x80x83xe2x80x83[Equation 3]
|JWf1| less than xcex94PD+tUDxe2x80x83xe2x80x83[Equation 4]
|"PHgr"MAX1|=xcex94PD+tUDxe2x80x83xe2x80x83[Equation 5]
It can be understood that the jitter and the maximum phase error can be reduced by decreasing the xcex94Pd and tUD, and also can be enhanced by other ways as shown in of FIGS. 2A and 2B. In other words, since, as shown in FIGS. 2A and 2B, the jitter windows are divergent from each other, the jitters can be reduced by as much as the amount in which two jitter windows overlap. FIG. 3 shows a block diagram of a conventional delay locked loop circuit for improving the jitter performance by using the facts. The main phase determining circuit 300, as shown in FIG. 3, includes two phase determining circuits 301 and 303, and a delay component 305 as essential components. Other characteristics are that the clock signal provided to an input signal terminal of the second phase determining circuit 303 passes through the delay component 305. In the description hereinafter, it is assumed that logic values of the signal PUSH or PULL become a logic high when the logic values are activated, and become a logic low when the values are not activated. Moreover, both of the signals PUSH and PULL, the outputs of one phase determining circuit cannot be logic high simultaneously. Only the signals must be determined as the logic high and or the logic low.
As shown in FIG. 3, the reference clock signal REF is directly provided to reference signal terminals REF of two phase determining circuits 301 and 303. Though an input signal IN is directly provided to an input signal terminal IN of the first phase determining circuit 301, a signal delayed as much as to is provided to an input signal terminal IN of the second phase determining circuit 303 via the delay component 305. Therefore, there is a time difference of as much as to between the signal provided to the input signal terminal IN of the first phase determining circuit 301 and the signal provided to the input signal terminal INxe2x80x2 of the second phase determining circuit 303. The phase push signal PUSH of the main phase determining circuit 300 is a result of performance of a logical product of the phase push signal PUSH1 of the first phase determining circuit 301 and the phase push signal PUSH2 of the second phase determining circuit 303 by using an AND gate 307. The phase pull signal PULL of the main phase determining circuit 300 is a result of performance of a logical product of the phase pull signal PULL1 of the first phase determining circuit 301 and the phase pull signal PULL2 of the second phase determining circuit 303 by using an AND gate 309.
Hereinafter, the principle of the operation of the circuit in FIG. 3 will be explained with reference to FIG. 4. As a matter of convenience for description, the error in the phase determining circuit is neglected. As shown in respective graphs of FIG. 4, the phase of the signal INxe2x80x2 is increased by to above the phase of the signal IN. First, since, in case of FIG. 4A, all phases of the input signals IN and INxe2x80x2 lead the phase of the reference signal REF, two phase determining circuits 301 and 303 would determine the case for the operation PUSH. In other words, since PUSH1 becomes high (PUSH1=high), PULL1 becomes low (PULL2=low), PUSH2 becomes high (PUSH2=high), and PULL2 becomes low (PULL2=low), finally it is determined to activate PUSH. In the case of FIG. 4B, since the input signal IN leads the reference signal REF and the input signal INxe2x80x2 lags the reference signal REF, the first phase determining circuit 301 determines the operation of PUSH and the second phase determining circuit 303 determines the operation of PULL. Namely, PUSH1 is high (PUSH1=high), PULL1 is low (PULL2=low), PUSH2 is low (PUSH2=low), and PULL2 is high (PULL2=high), final determination of the case of FIG. 4B becomes PUSH=PULL=low so that determination is not performed. Therefore, the delay change in the delay line does not occur. This state would be a locking state. Finally, in the case of FIG. 40, since both of phases of the input signals IN and INxe2x80x2 lag the phase of the reference signal REF, both of two phase determining circuits 301 and 303 determine PULL so that final determination becomes PULL. To sum up, if the determination results of two phase determining circuits 301 and 303 are same, the final determination prevails in the determination results, and if the determination results of two phase determining circuits 301 and 303 are different from each other, the final determination is assumed as a locking state so that the delay change in the delay line does not occur.
The jitter performance in this way is depicted in FIG. 5. Though it seems similar to that of FIG. 2 at a glance, since the main phase determining circuit 300 in FIG. 3, as shown as in FIG. 5A, has an effect to move the jitter window in the left direction by as much as to through the PUSH signal, the jitter window is converted into the following equation 6. The case of FIG. 5B is identical to the case of FIG. 2B and expressed by the equation 7. Namely, if, as described above, among the diverged jitter windows of FIGS. 5A and 5B, the jitter window in FIG. 5A can be shifted to left side so as to correspond to the jitter window of FIG. 5B, final jitter window becomes like one illustrated in FIG. 5C and expressed by equation 8, under the condition of making tD=tUD. The equation 8 shows that the jitter window is reduced by as much as tUD by being compared with the case of equation 4.
xe2x88x92xcex94PDxe2x88x92tD less than JWa2 less than xcex94PD+tUDxe2x88x92tDxe2x80x83xe2x80x83[Equation 6]
xe2x88x92xcex94PDxe2x88x92tUD less than JWb2 less than xcex94PDxe2x80x83xe2x80x83[Equation 7]
xe2x88x92xcex94PDxe2x88x92tUD less than JWf2 less than xcex94PDxe2x80x83xe2x80x83[Equation 8]
However, the main phase determining circuit 300 has drawbacks, as shown in FIG. 5C, in that the jitter window is not symmetric with respect to the reference signal. If the jitter window is identical to that as shown in FIG. 5C, in the case that the phase of the input signal (dIILCK in the circuit in FIG. 1) lags behind the phase of the reference signal (exCLK in the circuit of FIG. 1), the jitter performance is inferior relative to one in the case that the phase of the input signal leads the phase of the reference signal. Moreover, though the jitter window is reduced in the main phase determining circuit 300, the maximum phase error keeps unreduced magnitude of "PHgr"MAX=xe2x88x92(xcex94PD+tUD).
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a delay locked loop circuit with a jitter performance improved in reducing both an error of a phase determining circuit and a unit delay in a variable delay line.
Another object of the present invention is to provide a delay locked loop circuit with a jitter window being symmetric to a reference signal.
Still another object of the present invention is to provide a delay locked loop circuit with improved maximum phase error.
Still another object of the present invention is to provide a delay locked loop circuit with an improved jitter performance and a simple structure.
In order to accomplish this object, there is provided a delay locked loop circuit with a novel structure for improving a jitter performance. In accordance with the aspect of the present invention, the delay locked loop circuit includes a delay circuit for receiving an input clock signal and generating a delayed output clock signal. The delay circuit has a predetermined minimum variable delay, and the delayed output clock signal is delayed with respect to the input clock signal by a delay period to be determined in accordance with a delay control signal that is inputted into the delay circuit. Moreover, the delay locked loop circuit includes a phase determining block for receiving the input clock signal and the output clock signal, generating a phase pull signal when the phase of an input clock signal being delayed by as much as a first predetermined time period leads the phase of the output clock signal, and generating a phase push signal when a phase of the input clock signal lags behind the phase of an output clock signal being delayed by as much as a second predetermined time period, and a delay control circuit for generating the delay control signal for controlling the delay circuit to reduce the delay when the phase pull signal is received from the phase determining block and to increase the delay when the phase push signal is received from the phase determining block. The delay control circuit does not change the delay of the delay circuit when neither the phase pull signal nor the phase push signal is received from the phase determining block. According to the aspects of the delay locked loop circuit of the present invention, the jitter performance can be enhanced while remaining the minimum variable delay of the delay circuit. Moreover, it is possible to obtain a jitter window symmetric to the reference signal as well as to reduce the maximum phase error. If a delay locked loop circuit having these characteristics is realized, there is advantage of being able to provide a delay locked loop circuit of even simpler structure.
In accordance with another aspect of the present invention, the phase determining block preferably includes a first delay section for receiving the input clock signal and generating an input clock signal delayed by as much as the first predetermined time period, a second delay section for receiving the output clock signal and generating an output clock signal delayed by as much as the second predetermined time period, a first phase determining section for receiving the delayed input clock signal and the output clock signal, and for generating the phase pull signal when the phase of the delayed input clock signal leads the phase of the output clock signal, and a second phase determining section for receiving the input clock signal and the delayed output clock signal and generating the phase push signal when the phase of the input clock signal lags behind the phase of the delayed output clock signal. By doing so, the phase determining block can be constructed with minimal structural elements.
Moreover, the phase determining block can be constructed with a first delay section for receiving the input clock signal and generating an input clock signal delayed by as much as the first predetermined time period, a second delay section for receiving the output clock signal and generating an output clock signal delayed by as much as the second predetermined time period, a first phase determining section for receiving the delayed input clock signal and the output clock signal, and for generating a first phase pull signal when the phase of the delayed input clock signal leads the phase of the output clock signal, and a first phase push signal when the phase of the delayed input clock signal lags behind the phase of the output clock signal, a second phase determining section for receiving the input clock signal and the delayed output clock signal, and for generating a second phase pull signal when the phase of the input clock signal leads the phase of the delayed output clock signal, and a second phase push signal when the phase of the input clock signal lags behind the phase of the delayed output clock signal, a third phase determining section for receiving the input clock signal and the output clock signal, and for generating a third phase pull signal when the phase of the input clock signal leads the phase of the output clock signal, and a third phase push signal when the phase of the input clock signal lags the phase of the output clock signal, a first logic product means for generating the phase pull signal by logically multiplying the first through the third phase pull signals, and a second logic product means for generating the phase push signal by logically multiplying the first through the third phase push signals.
Preferably, the first time period is a half of the minimum variable delay. Moreover, the second predetermined time period is a half of the minimum variable delay. When the first and second predetermined time periods are equal to a half of the minimum variable delay, the jitter windows of the signal PUSH and PULL can overlap well, and since the final jitter window is symmetric to the reference signal, optimal jitter performance can be obtained.